1. Field of the Invention
The present invention generally relates to digital data memory circuits and more particularly relates to improvements to CMOS static random access memory.
2. Description of the Prior Art
Various early main memory storage devices tended to utilize mechanical motion for access. Because these devices were so slow, they were soon replaced by electromagnetic systems, such as magnetic core memory. These technologies dominated in main frame computer design until the early 70's when various semiconductor techniques became dense enough and cheap enough to enter large scale usage.
Although bipolar devices tend to have an inherent speed advantage over metal oxide semiconductors (MOS), the lower power requirements of the latter proved particularly attractive. Complementary symmetry metal oxide semiconductors (CMOS) tend to have the lowest quiescent power requirements within the class. For that reason, CMOS is a particularly attractive technology for large scale static random access memories.
Many CMOS static random access memories (SRAM's) utilize four transistors per storage cell. However, due to the advantages of employing pull up transistors for each side of the cell, the six transistor cell approach is gaining in popularity. These advantages are higher operational stability, higher alpha-particle immunity, and a simpler process, which is more similar to the process for random logic circuit fabrication.
A primary disadvantage of the six transistor cell CMOS SRAM is that certain open circuit failures in the pull up circuitry can appear as intermittent or soft failures. Whereas the analogous problem of open pull up resistors can also occur with four transistor cells, the greater popularity and complexity of the six transistor cells makes the problem more acute. Because such faults do not result in a hard failure, testing and failure analysis have proven particularly difficult. Often times extreme temperature cycling and sophisticated timing functions have been utilized during the manufacturing process, and sometimes all of the defects are still not located. In addition, such techniques are particularly difficult if not impossible to employ in the field with operational main frames.
An approach to testing is suggested in "Soft-Defect Detection (SDD) Technique for a High-Reliability CMOS SRAM", by Clinton Kuo, et al. in IEEE Journal of Solid-State Circuits, Volume 25, No. 1, February 1990. The Kuo et al. approach attempts to perform complete circuit by circuit analysis of each current path within the cell. The technique requires the addition of substantial specialized control and addressing circuitry. However, the greatest disadvantage of the method is the relatively long time frame needed to run the six separate tests for each cell.